If I want to be able program the flash in circuit, I need to be able to control the upper bits of the flash addressable range which means, I should disable mapping in the map CPLD on BUSACK low. Or--I need to be be able to control the MCU CPLD which means I need to control nIORQ, nMREQ, and nM1 as well as nHALT. Well, that's all way to complicated. So I'll see if I can add BUSACK to the MCU CPLD..... Running out of pins. I can't have too much stuff occurring to me....
Then I'll make the flash bank come from the Arduino. I plan to use the top bit of the address range choose the flash.
Dammit! I just realized, I need to invert it for CS on the SRAM..... And dammit again, I need to only enable CS on flash and SRAM when MREQ is low.....
So, I have 2 pins left over I can use. reduce the top bit from map---, that makes 3. Then add in nBUSACK, nCS0, and nCS1. These are essentially the top bit of the mapping but only go low on nMREQ low. I hope it fits... I hope I can constrain the pins....
This will require a little tweaking to the design. Such is engineering....
Update: I'm overcomplicating the BUSACK part. RESET is good enough. I need to control RESET from the Arduino.
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