I have been dealing with my board with its attached Arduino. And while I need the Arduino to unbrick the board, I don't need it for normal operation.
It took me a while to figure out what was going on. The behavior depended on whether the start up function did a run from RAM. That is, copy the current bank 0 into a RAM bank and then swap that RAM bank into bank 0. This is needed to program flash since programming flash requires no access from flash while it's programming. It is also necessary for setting breakpoints as a breakpoint is set by putting an 'rst 20h' instruction where the breakpoint belongs.
So when I was trying to run from RAM, it just bricked the computer. I finally recalled a choice I made to keep the CPLD from getting too complex. RESET changes the current banks, but I decided to rely on SW to set the next bank registers. But the runFromRAM function was just assuming that banks 2 and 3 were the same as the registers that specify the next banks 2 and 3. This is an invalid assumption. So, I added a memBankInit function that copies the current bank registers into the next bank registers.
Sunday, November 8, 2015
Friday, October 30, 2015
Board Stopped Working
So, every so often my board decides to stop working. While it's a problem, solving problems is fun. I did load a new image into the 0 bank that was aggressively optimized. So it could be that. I did reset after loading, but neglected to power cycle. When I turned it on last night, nothing.
So I decided to restore an old image--but the Arduino program wasn't working. I am having trouble with wire wraps to bare copper wires. So I decided to redo the Arduino connector. I had been meaning to anyway, since I don't need the Arduino anymore except with this happens. I also wanted to mount an SD card slot for accessing an SD card which could potentially give be a whole chunk of flash depending on if I can drivers to fit. I probably would use as a block addressable device rather than with a file system. Fortunately, linux has a command called "dd" which would let me do that.
Here are pictures of the new sections. The first is the connector with the Arduino already connected with the red wires. It also has the SD card slot.
This is the back. I had to solder the wires to the connector and the insulation is a bit melted, so I'm hoping I won't have any shorts. Right now I don't.
Now, I'm off to see if I can get the flash to program again....
So I decided to restore an old image--but the Arduino program wasn't working. I am having trouble with wire wraps to bare copper wires. So I decided to redo the Arduino connector. I had been meaning to anyway, since I don't need the Arduino anymore except with this happens. I also wanted to mount an SD card slot for accessing an SD card which could potentially give be a whole chunk of flash depending on if I can drivers to fit. I probably would use as a block addressable device rather than with a file system. Fortunately, linux has a command called "dd" which would let me do that.
Here are pictures of the new sections. The first is the connector with the Arduino already connected with the red wires. It also has the SD card slot.
This is the back. I had to solder the wires to the connector and the insulation is a bit melted, so I'm hoping I won't have any shorts. Right now I don't.
Now, I'm off to see if I can get the flash to program again....
Wednesday, October 28, 2015
Disassembler in Action
I have a mechanism for attaching the disassembler to the breakpoint prompt. The applet in bank 1 has to have the disassember code because it's too big to fit with everything in bank 0. So, the address of the function is placed at 0x0024 and if that location is not 0, it is called. This has to be registered in main, so when the breakpoint occurs at the beginning of main, the disassember is not hooked up yet. But, see the output below. Once the debugger gets to 4074 disassembly is possible. The command is 'z' with optional number of instructions and then an optional start address.
I still have a lot of diagnostic stuff in the breakpoint code that I'm ready to remove (e.g. "Set BP0 @ 4062 (6-0)" and "RST 20 to dd @ 4066").
OK, I cleaned up the diagnostic stuff. Here is what it looks like now:
Mark Hamann's Z80 Computer
App Build: 20:59:21 Oct 1 2015
BSP Build: 20:59:19 Oct 1 2015
C Lib Build: 20:08:20 Sep 30 2015
Menu
1: dir
2: run applet
3: program intel hex
4: utils menu
5: drivers menu
> 3
In IHX program mode. Ensure that HW flow control is on.
Flash bank to program (0-f)? 4
Is this an applet (y/n)? n
Not erased. Erase (y/n)? y
Now, paste the .ihx contents
The mode will end on the :00000001FF
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffDone!
> 2
Applet bank? (2-f)? c
Loading C vector bank 4 and applet bank c for version 0103 (ok=0)
Flash to RAM...
Prepping banks...
About to jump...
Set BP0 @ 4060 (6-0)
RST 20 to dd @ 4060
Breaking at main()
4060 e7
RST 20 from dd @ 4060
(brk @ 4060)> n
branch 00
Set BP0 @ 4062 (6-0)
RST 20 to dd @ 4062
RST 20 from dd @ 4062
(brk @ 4062)>
(brk @ 4062)> n
branch 00
Set BP0 @ 4066 (6-0)
RST 20 to dd @ 4066
RST 20 from dd @ 4066
(brk @ 4066)> n
branch 00
Set BP0 @ 4068 (6-0)
RST 20 to 21 @ 4068
RST 20 from 21 @ 4068
(brk @ 4068)> n
branch 00
Set BP0 @ 406b (6-0)
RST 20 to 39 @ 406b
RST 20 from 39 @ 406b
(brk @ 406b)> n
branch 00
Set BP0 @ 406c (6-0)
RST 20 to f9 @ 406c
RST 20 from f9 @ 406c
(brk @ 406c)> n
branch 00
Set BP0 @ 406d (6-0)
RST 20 to 21 @ 406d
RST 20 from 21 @ 406d
(brk @ 406d)> n
branch 00
Set BP0 @ 4070 (6-0)
RST 20 to e5 @ 4070
RST 20 from e5 @ 4070
(brk @ 4070)> z
(brk @ 4070)> n
branch 00
Set BP0 @ 4071 (6-0)
RST 20 to cd @ 4071
RST 20 from cd @ 4071
(brk @ 4071)> z
(brk @ 4071)> n
branch 18
Set BP0 @ 4074 (6-0)
RST 20 to 21 @ 4074
RST 20 from 21 @ 4074
(brk @ 4074)> z
4074: ld hl, 8080h
4077: ex (sp), hl
4078: call 3f23h
407b: pop af
407c: call 3f1dh
407f: ld hl, 007fh
4082: push hl
4083: call 3f11h
(brk @ 4074)> z 10 0
0: jp 0069h
3: rst 38h
4: rst 38h
5: rst 38h
6: rst 38h
7: rst 38h
8: jp 0db1h
b: rst 38h
c: rst 38h
d: rst 38h
e: rst 38h
f: rst 38h
10: jp 0dc2h
13: rst 38h
14: rst 38h
15: rst 38h
(brk @ 4074)> n
branch 00
Set BP0 @ 4077 (6-0)
RST 20 to e3 @ 4077
RST 20 from e3 @ 4077
(brk @ 4077)> z
4077: ex (sp), hl
4078: call 3f23h
407b: pop af
407c: call 3f1dh
407f: ld hl, 007fh
4082: push hl
4083: call 3f11h
4086: pop af
(brk @ 4077)> n
branch 00
Set BP0 @ 4078 (6-0)
RST 20 to cd @ 4078
RST 20 from cd @ 4078
(brk @ 4078)> n
branch 18
Set BP0 @ 407b (6-0)
RST 20 to f1 @ 407b
RST 20 from f1 @ 407b
(brk @ 407b)> z
407b: pop af
407c: call 3f1dh
407f: ld hl, 007fh
4082: push hl
4083: call 3f11h
4086: pop af
4087: ld hl, 0000h
408a: add hl, sp
(brk @ 407b)> c
branch 00
Set BP0 @ 407c (a-1)
RST 20 to cd @ 407c
RST 20 from cd @ 407cOK, I cleaned up the diagnostic stuff. Here is what it looks like now:
Menu
1: dir
2: run applet
3: program intel hex
4: utils menu
5: drivers menu
> 3
In IHX program mode. Ensure that HW flow control is on.
Flash bank to program (0-f)? 4
Is this an applet (y/n)? n
Not erased. Erase (y/n)? y
Now, paste the .ihx contents
The mode will end on the :00000001FF
fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffDone!
> 2
Applet bank? (2-f)? c
Loading C vector bank 4 and applet bank c for version 0103 (ok=0)
Flash to RAM...
Prepping banks...
About to jump...
Breaking at main()
4060 e7
(brk @ 4060)> n
(brk @ 4062)> n
(brk @ 4066)> n
(brk @ 4068)> n
(brk @ 406b)> n
(brk @ 406c)> n
(brk @ 406d)> n
(brk @ 4070)> n
(brk @ 4071)> n
(brk @ 4074)> n
(brk @ 4077)> z
4077: ex (sp), hl
4078: call 3f23h
407b: pop af
407c: call 3f1dh
407f: ld hl, 007fh
4082: push hl
4083: call 3f11h
4086: pop af
(brk @ 4077)> n
(brk @ 4078)> n
(brk @ 407b)> n
(brk @ 407c)> n
(brk @ 407f)> n
(brk @ 4082)> n
(brk @ 4083)> n
(brk @ 4086)> z
4086: pop af
4087: ld hl, 0000h
408a: add hl, sp
408b: ld d, l
408c: ld e, h
408d: ld bc, 40c7h
4090: push hl
4091: push de
(brk @ 4086)>
Monday, October 26, 2015
Disassembly
In order to make debugging easier, I thought it might to have a disassembler. It's fairly table driven. It needs a lot of work still. I think it disassembles valid instructions, but doesn't guarantee that invalid instructions are handled in any particular way. By valid, I mean the officially documented instructions. It is not optimized for speed. Rather, my goal was code size. Whether I met that or not is something I'm wondering. All the little special cases add code size.
Anyone needing a Z-80 disassembler is free to use what they want from this.
Anyone needing a Z-80 disassembler is free to use what they want from this.
// Associate shiftMask to a StartInfo
struct ShiftMaskAndIndexStartInfo {
// upper nibble is shift amount. Bottom nibble is mask
uint8_t shiftMaskInfo;
// A start index
uint8_t indexStart;
};
// Information to create an instruction
struct InstructionInfo
{
// 8 bit mask of relevant bits
uint8_t mask;
// expected value after anding with mask
uint8_t value;
// 7-6: type 5-0: index
uint8_t opcodeInfo;
// arg0 info
uint8_t argInfoIndex0;
// arg1 info
uint8_t argInfoIndex1;
};
// Opcode builder
struct OpcodeBuildInfo {
// 8 bit mask of relevant bits
uint8_t mask;
// Expected value after anding with mask
uint8_t value;
// Letter to append if (b & mask) == value
char letter;
};
// Keep synched with InstructionTableArray
enum InstructionTableIndices
{
TABLE_MAIN_00,
TABLE_MAIN_40,
TABLE_MAIN_80,
TABLE_MAIN_C0,
TABLE_CB,
TABLE_ED,
TABLE_COUNT
};
// keep synched with LiteralStringArray
enum LiteralStringIndices {
DA_LIT_Q,
DA_LIT_nop,
DA_LIT_djnz,
DA_LIT_jr,
DA_LIT_ld,
DA_LIT_add,
DA_LIT_ex,
DA_LIT_halt,
DA_LIT_ret,
DA_LIT_call,
DA_LIT_jp,
DA_LIT_exx,
DA_LIT_rst,
DA_LIT_neg,
DA_LIT_reti,
DA_LIT_retn,
DA_LIT_im,
DA_LIT_inc,
DA_LIT_dec,
DA_LIT_adc,
DA_LIT_sub,
DA_LIT_sbc,
DA_LIT_and,
DA_LIT_xor,
DA_LIT_or,
DA_LIT_cp,
DA_LIT_daa,
DA_LIT_cpl,
DA_LIT_scf,
DA_LIT_ccf,
DA_LIT_pop,
DA_LIT_push,
DA_LIT_out,
DA_LIT_in,
DA_LIT_di,
DA_LIT_ei,
DA_LIT_bit,
DA_LIT_set,
DA_LIT_res,
DA_LIT_nz,
DA_LIT_z,
DA_LIT_nc,
DA_LIT_c,
DA_LIT_po,
DA_LIT_pe,
DA_LIT_p,
DA_LIT_m,
DA_LIT_bc,
DA_LIT_de,
DA_LIT_hl,
DA_LIT_ix,
DA_LIT_iy,
DA_LIT_sp,
DA_LIT_af,
DA_LIT_a,
DA_LIT_b,
DA_LIT_d,
DA_LIT_e,
DA_LIT_h,
DA_LIT_l,
DA_LIT_i,
DA_LIT_r,
DA_LIT_af_alt,
DA_LIT_COUNT
};
// keep synced with enum DisassembleLiteralIndices
static const char* const LiteralStringArray[DA_LIT_COUNT] =
{
"?",
"nop",
"djnz",
"jr",
"ld",
"add",
"ex",
"halt",
"ret",
"call",
"jp",
"exx",
"rst",
"neg",
"reti",
"retn",
"im",
"inc",
"dec",
"adc",
"sub",
"sbc",
"and",
"xor",
"or",
"cp",
"daa",
"cpl",
"scf",
"ccf",
"pop",
"push",
"out",
"in",
"di",
"ei",
"bit",
"set",
"res",
"nz",
"z",
"nc",
"c",
"po",
"pe",
"p",
"m",
"bc",
"de",
"hl",
"ix",
"iy",
"sp",
"af",
"a",
"b",
"d",
"e",
"h",
"l",
"i",
"r",
"af'"
};
/*
0: @alu : add, adc, sub, sbc, and, xor, or, cp
1 : @bitsetres : -, bit, set, res
2 : @daacplscfccf : daa, cpl, scf, ccf
3 : @incdec : inc, dec
4 : @poppush : pop, push
5 : @outin : out, in
6 : @inout : in, out
7 : @diei : di, ei
8 : @sbcadc : sbc, adc
*/
enum OpcodeByMaskInfoIndices
{
OPCODE_MASKABLE_ALU, // 10@@ @rrr -- 11@@ @110
OPCODE_MASKABLE_BIT, // @@## #rrr
OPCODE_MASKABLE_DAA, // 001@ @111
OPCODE_MASKABLE_INC_RRS, // 00rr @011
OPCODE_MASKABLE_INC_R, // 00rr r10@
OPCODE_MASKABLE_POP, // 11rr 0@01
OPCODE_MASKABLE_INOUT, // 01rr r00@
OPCODE_MASKABLE_OUTIN, // 1110 @011
OPCODE_MASKABLE_DIEI, // 1111 @011
OPCODE_MASKABLE_SBC, // 01rr @010
OPCODE_MASKABLE_COUNT,
};
enum OpcodeByMaskStartIndices
{
MASKABLE_ALU = 0,
MASKABLE_BIT = MASKABLE_ALU + 8-1, // first element of bit can't exist, so collapse
MASKABLE_DAA = MASKABLE_BIT + 4,
MASKABLE_INC = MASKABLE_DAA + 4,
MASKABLE_POP = MASKABLE_INC + 2,
MASKABLE_INOUT = MASKABLE_POP + 2,
MASKABLE_OUTIN = MASKABLE_INOUT + 2 - 1,
MASKABLE_DIEI = MASKABLE_OUTIN + 2,
MASKABLE_SBC = MASKABLE_DIEI + 2,
MASKABLE_ARRAY_COUNT = MASKABLE_SBC + 2
};
static const struct ShiftMaskAndIndexStartInfo OpcodeByMaskShiftMaskArray[OPCODE_MASKABLE_COUNT] =
{
{
0x37, MASKABLE_ALU
},
{
0x63, MASKABLE_BIT
},
{
0x33, MASKABLE_DAA
},
{ // r
0x31, MASKABLE_INC
},
{ // rrs
0x01, MASKABLE_INC
},
{
0x21, MASKABLE_POP
},
{
0x01, MASKABLE_INOUT
},
{
0x31, MASKABLE_OUTIN
},
{
0x31, MASKABLE_DIEI
},
{
0x31, MASKABLE_SBC
},
};
static const uint8_t OpcodeByMaskArray[MASKABLE_ARRAY_COUNT] =
{
// MASKABLE_ALU = 0
DA_LIT_add, // 0
DA_LIT_adc,
DA_LIT_sub,
DA_LIT_sbc,
DA_LIT_and,
DA_LIT_xor,
DA_LIT_or,
// MASKABLE_BIT = 7
DA_LIT_cp,
DA_LIT_bit, // 8
DA_LIT_res,
DA_LIT_set,
// MASKABLE_DAA
DA_LIT_daa, // 11
DA_LIT_cpl,
DA_LIT_scf,
DA_LIT_ccf,
// MASKABLE_INC
DA_LIT_inc, // 15
DA_LIT_dec,
// MASKABLE_POP
DA_LIT_pop, // 17
DA_LIT_push,
// MASKABLE_INOUT
DA_LIT_in, // 19
// MASKABLE_OUTIN
DA_LIT_out, // 20
DA_LIT_in,
// MASKABLE_EIDI
DA_LIT_di, // 22
DA_LIT_ei,
// MASKABLE_SBC
DA_LIT_sbc, // 24
DA_LIT_adc
};
// ROTATE Main-00-00; ED-80-00; CB-02-00 "r"
// SHIFT CB-02-02 "s"
// LD ED-07-00 "ld"
// CP ED-07-01 "cp"
// IN ED-07-02 "in"
// OT ED-07-03 "ot
// CARRY MAIN/CB-01-01 "c"
// LOGIGAL CB-03-03 "l"
// ARITH/Acc CB-03-02 "a"
// LEFT Main-08-00; "l"
// RIGHT Main-08-08; "r"
// INC ED-88-80 "i"
// DEC ED-88-88 "d"
// REPEAT ED-f0-b0 "r"
enum OpcodeByBuilderIndices
{
OPCODE_BUILD_RLCA,
OPCODE_BUILD_RRD,
OPCODE_BUILD_LDI,
OPCODE_BUILD_RLC
};
// sync with OpcodeBuilderArray and OpcodeByBuilderIndices
static const uint8_t OpcodeBuilderIndexToOpcodeBuilderArrayStartIndex[] = {
0,
6,
11,
24,
33
};
// synch with OpcodeBuilderIndexToOpcodeBuilderArrayStartIndex
static const struct OpcodeBuildInfo OpcodeBuilderArray[32] = {
//MAIN table
//{
// main = 0 (5)
{ 0x00, 0x00, 'r' },
{ 0x08, 0x00, 'l' },
{ 0x08, 0x08, 'r' },
{ 0x10, 0x00, 'c' },
{ 0x00, 0x00, 'a' },
{ 0x00, 0x00, 0 },
//},
// ED table
//{
{ 0x00, 0x00, 'r' },
{ 0xc8, 0x40, 'r' },
{ 0xc8, 0x48, 'l' },
{ 0x00, 0x00, 'd' },
{ 0x00, 0x00, 0 },
//},
//{
{ 0xc7, 0x80, 'l' },
{ 0xc7, 0x80, 'd' },
{ 0xc7, 0x81, 'c' },
{ 0xc7, 0x81, 'p' },
{ 0xc7, 0x82, 'i' },
{ 0xc7, 0x82, 'n' },
{ 0xc7, 0x83, 'o' },
{ 0xf7, 0xa3, 'u' },
{ 0xc7, 0x83, 't' },
{ 0x88, 0x80, 'i' },
{ 0x88, 0x88, 'd' },
{ 0xf0, 0xb0, 'r' },
{ 0x00, 0x00, 0 },
//},
// CB table
//{
{ 0x20, 0x00, 'r' },
{ 0x20, 0x20, 's' },
{ 0x08, 0x00, 'l' },
{ 0x08, 0x08, 'r' },
{ 0x30, 0x00, 'c' },
{ 0x30, 0x20, 'a' },
{ 0x30, 0x30, 'l' },
{ 0x00, 0x00, 0 },
//}
};
#define ARG_TYPE_SPECIAL (0x00)
#define ARG_TYPE_LIT (0x10)
#define ARG_TYPE_MASK (0x20)
#define ARG_TYPE_SWAPPABLE (0x40)
#define ARG_TYPE_CONTENTS (0x80)
enum ArgByMaskStartIndices
{
ARG_ARR_FL = 0,
ARG_ARR_RRS = ARG_ARR_FL + 8,
ARG_ARR_RRA = ARG_ARR_RRS + 4,
ARG_ARR_HLA = ARG_ARR_RRA + 4,
ARG_ARR_R = ARG_ARR_HLA + 2,
ARG_ARR_IR = ARG_ARR_R + 8,
ARG_ARR_IM = ARG_ARR_IR + 2,
ARG_ARR_COUNT = ARG_ARR_IM + 4
};
static const uint8_t ArgByMaskArray[ARG_ARR_COUNT] =
{
DA_LIT_nz, // 0
DA_LIT_z,
DA_LIT_nc,
DA_LIT_c,
DA_LIT_po,
DA_LIT_pe,
DA_LIT_p,
DA_LIT_m,
DA_LIT_bc, // 8
DA_LIT_de,
DA_LIT_hl,
DA_LIT_sp,
DA_LIT_bc, // 12
DA_LIT_de,
DA_LIT_hl,
DA_LIT_af,
DA_LIT_hl, // 16
DA_LIT_a,
DA_LIT_b, // 18
DA_LIT_c,
DA_LIT_d,
DA_LIT_e,
DA_LIT_h,
DA_LIT_l,
DA_LIT_hl | ARG_TYPE_CONTENTS,
DA_LIT_a,
DA_LIT_i, // 42
DA_LIT_r,
};
/*
//
#define ARG_TYPE_MASK (0x01)
// mask, index
#define ARG_TYPE_LIT (0x02)
// (int8_t)(*(pc)) + pc; pc++;
#define ARG_TYPE_REL (0x03)
#define ARG_TYPE_IMM8 (0x04)
#define ARG_TYPE_IMM16 (0x05)
#define ARG_TYPE_ASCII (0x06)
#define ARG_TYPE_RST (0x07)
*/
// index to next table ED/CB/DDFD
#define OPCODE_TYPE_LIT (0x00)
// index
#define OPCODE_TYPE_ARR (0x40)
// mask, index
#define OPCODE_TYPE_BUILD (0x80)
// index
#define OPCODE_TYPE_SUB (0xc0)
// [8:mask],[8:val],[2:opcode, 6:index0] [1: swappable 3: arg0 3: arg1]
// index 0 is literal index for literal, or maskables index for maskable. For build, the build index
// swapbit is there only if swappable. Swap bit is 3 for main, 4 for ED
// arginfo is:
// if 00 no arg
// if 01 mask [8: mask(-sss-mmm)] [8: arg_arr index] or 3bit is mask index, 5 bits is arg_arr index
// if 02 lit [8: lit index]
// if 03 uint8 get next byte
// if 04 RelAddr get next byte, add to location
// if 05 uint16 get next word
// bit 8 swappable
enum ArgInfo {
ARG_INFO_NONE,
ARG_INFO_rel, // 1
ARG_INFO_imm8,
ARG_INFO_imm16,
ARG_INFO_bit,
ARG_INFO_rst,
ARG_INFO_im,
ARG_INFO_LIT_a = ARG_TYPE_LIT, // 4
ARG_INFO_LIT_af,
ARG_INFO_LIT_af_alt,
ARG_INFO_LIT_c,
ARG_INFO_LIT_de,
ARG_INFO_LIT_hl, // 8
ARG_INFO_LIT_sp,
//ARG_INFO_LIT_q,
ARG_INFO_MASK_30_RRS = ARG_TYPE_MASK,
ARG_INFO_MASK_30_RRA,
ARG_INFO_MASK_07_R,
ARG_INFO_MASK_38_R,
ARG_INFO_MASK_18_FL,
ARG_INFO_MASK_38_FL,
ARG_INFO_MASK_08_IR,
};
/*
enum ArgMaskIndex {
ARG_MASK_30_RRS,
ARG_MASK_30_RRA,
ARG_MASK_07_R,
ARG_MASK_38_R,
ARG_MASK_30_FL,
ARG_MASK_38_FL,
ARG_MASK_38_RST,
ARG_MASK_80_IR,
ARG_MASK_COUNT,
};
*/
// sync with ArgInfo from ARG_TYPE_LIT
static const uint8_t ArgByLitIndexToStringLiteralIndex[] = {
DA_LIT_a,
DA_LIT_af,
DA_LIT_af_alt,
DA_LIT_c,
DA_LIT_de,
DA_LIT_hl,
DA_LIT_sp
};
// sync with ArgInfo from ARG_TYPE_MASK
static const struct ShiftMaskAndIndexStartInfo ArgShiftMaskStartIndex[] =
{
{ /*0x30*/ 0x43, ARG_ARR_RRS },
{ /*0x30*/ 0x43, ARG_ARR_RRA },
{ /*0x07*/ 0x07, ARG_ARR_R },
{ /*0x38*/ 0x37, ARG_ARR_R },
{ /*0x18*/ 0x33, ARG_ARR_FL },
{ /*0x38*/ 0x37, ARG_ARR_FL },
{ /*0x08*/ 0x31, ARG_ARR_IR },
};
char* buildOpcode(uint8_t opcode, uint8_t table, char* line)
{
const struct OpcodeBuildInfo* cand = &OpcodeBuilderArray[OpcodeBuilderIndexToOpcodeBuilderArrayStartIndex[table]];
while (cand->letter != 0)
{
if ((opcode & cand->mask) == cand->value)
{
*line++ = cand->letter;
}
cand++;
}
*line++ = '\0';
return line;
}
static const struct InstructionInfo InstructionInfoTableMain_00[] =
{
{
0xff,
0x00,
DA_LIT_nop | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE,
},
{
0xff,
0x10,
DA_LIT_djnz | OPCODE_TYPE_LIT,
ARG_INFO_rel,
ARG_INFO_NONE
},
{
0xe7,
0x20,
DA_LIT_jr | OPCODE_TYPE_LIT,
ARG_INFO_MASK_18_FL,
ARG_INFO_rel,
},
{
0xcf,
0x01,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_MASK_30_RRS,
ARG_INFO_imm16
},
{
0xe7,
0x02,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_MASK_30_RRS | ARG_TYPE_SWAPPABLE | ARG_TYPE_CONTENTS, // swap on 0x08
ARG_INFO_LIT_a
},
{
0xcf,
0x09,
DA_LIT_add | OPCODE_TYPE_LIT,
ARG_INFO_LIT_hl,
ARG_INFO_MASK_30_RRS
},
{
0xf7,
0x32,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_imm16 | ARG_TYPE_SWAPPABLE | ARG_TYPE_CONTENTS, // swap on 0x08
ARG_INFO_LIT_a
},
{
0xf7,
0x22,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_imm16 | ARG_TYPE_SWAPPABLE | ARG_TYPE_CONTENTS, // swap on 0x08
ARG_INFO_LIT_hl
},
{
0xc7,
0x03,
OPCODE_MASKABLE_INC_RRS | OPCODE_TYPE_ARR,
ARG_INFO_MASK_30_RRS,
ARG_INFO_NONE
},
{
0xc6,
0x04,
OPCODE_MASKABLE_INC_R | OPCODE_TYPE_ARR,
ARG_INFO_MASK_38_R,
ARG_INFO_NONE
},
{
0xc7,
0x06,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_MASK_38_R,
ARG_INFO_imm8
},
{
0xff,
0x08,
DA_LIT_ex | OPCODE_TYPE_LIT,
ARG_INFO_LIT_af,
ARG_INFO_LIT_af_alt
},
{
0xff,
0x18,
DA_LIT_jr | OPCODE_TYPE_LIT,
ARG_INFO_rel,
ARG_INFO_NONE
},
{
0xe7,
0x27,
OPCODE_MASKABLE_DAA | OPCODE_TYPE_ARR,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xe7,
0x07,
OPCODE_BUILD_RLCA | OPCODE_TYPE_BUILD,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0x00,
0x00,
DA_LIT_Q | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
}
};
static const struct InstructionInfo InstructionInfoTableMain_40[] =
{
{ // Must be before ld r,r
0xff,
0x76,
DA_LIT_halt | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{ // Must be after halt
0xc0,
0x40,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_MASK_38_R,
ARG_INFO_MASK_07_R
},
{
0x00,
0x00,
DA_LIT_Q | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
}
};
static const struct InstructionInfo InstructionInfoTableMain_80[] =
{
{
0xc0,
0x80,
OPCODE_MASKABLE_ALU | OPCODE_TYPE_ARR,
ARG_INFO_LIT_a,
ARG_INFO_MASK_07_R
},
{
0x00,
0x00,
DA_LIT_Q | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
}
};
static const struct InstructionInfo InstructionInfoTableMain_c0[] =
{
{
0xc7,
0xc0,
DA_LIT_ret | OPCODE_TYPE_LIT,
ARG_INFO_MASK_38_FL,
ARG_INFO_NONE
},
{
0xff,
0xcd,
DA_LIT_call | OPCODE_TYPE_LIT,
ARG_INFO_imm16,
ARG_INFO_NONE
},
{
0xff,
0xc3,
DA_LIT_jp | OPCODE_TYPE_LIT,
ARG_INFO_imm16,
ARG_INFO_NONE
},
{
0xff,
0xe9,
DA_LIT_jp | OPCODE_TYPE_LIT,
ARG_INFO_LIT_hl | ARG_TYPE_CONTENTS,
ARG_INFO_NONE
},
{
0xff,
0xf9,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_LIT_sp,
ARG_INFO_LIT_hl
},
{
0xcb,
0xc1,
OPCODE_MASKABLE_POP | OPCODE_TYPE_ARR,
ARG_INFO_MASK_30_RRA,
ARG_INFO_NONE
},
{
0xff,
0xc9,
DA_LIT_ret | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xff,
0xd9,
DA_LIT_exx | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xc7,
0xc2,
DA_LIT_jp | OPCODE_TYPE_LIT,
ARG_INFO_MASK_38_FL,
ARG_INFO_imm16
},
{
0xc7,
0xc4,
DA_LIT_call | OPCODE_TYPE_LIT,
ARG_INFO_MASK_38_FL,
ARG_INFO_imm16
},
{
0xc7,
0xc7,
DA_LIT_rst | OPCODE_TYPE_LIT,
ARG_INFO_rst,
ARG_INFO_NONE
},
{
0xc7,
0xc6,
OPCODE_MASKABLE_ALU | OPCODE_TYPE_ARR,
ARG_INFO_LIT_a,
ARG_INFO_imm8
},
{
0xf7,
0xd3,
OPCODE_MASKABLE_OUTIN | OPCODE_TYPE_ARR,
ARG_INFO_imm8 | ARG_TYPE_CONTENTS | ARG_TYPE_SWAPPABLE, // swap on 0x08
ARG_INFO_LIT_a
},
{
0xf7,
0xf3,
OPCODE_MASKABLE_DIEI | OPCODE_TYPE_ARR,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xff,
0xe3,
DA_LIT_ex | OPCODE_TYPE_LIT,
ARG_INFO_LIT_sp | ARG_TYPE_CONTENTS,
ARG_INFO_LIT_hl
},
{
0xff,
0xeb,
DA_LIT_ex | OPCODE_TYPE_LIT,
ARG_INFO_LIT_de,
ARG_INFO_LIT_hl
},
{
0xff,
0xcb,
TABLE_CB | OPCODE_TYPE_SUB,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xff,
0xed,
TABLE_ED | OPCODE_TYPE_SUB,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xfd,
0xfd,
0 | OPCODE_TYPE_SUB,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0x00,
0x00,
DA_LIT_Q | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
}
};
static const struct InstructionInfo InstructionInfoTableCB[] =
{
// CB
{
0xc0,
0x00,
OPCODE_BUILD_RLC | OPCODE_TYPE_BUILD,
ARG_INFO_MASK_07_R,
ARG_INFO_NONE
},
{
0x00,
0x00,
OPCODE_MASKABLE_BIT | OPCODE_TYPE_ARR,
ARG_INFO_bit,
ARG_INFO_MASK_07_R
},
{
0x00,
0x00,
DA_LIT_Q | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
}
};
static const struct InstructionInfo InstructionInfoTableED[] =
{
// ED
{
0xc6,
0x40,
OPCODE_MASKABLE_INOUT | OPCODE_TYPE_ARR,
ARG_INFO_MASK_38_R | ARG_TYPE_SWAPPABLE, // TODO swap on 0x01
ARG_INFO_LIT_c | ARG_TYPE_CONTENTS
},
{
0xc7,
0x42,
OPCODE_MASKABLE_SBC | OPCODE_TYPE_ARR,
ARG_INFO_LIT_hl,
ARG_INFO_MASK_30_RRS
},
{
0xc7,
0x43,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_imm16 | ARG_TYPE_CONTENTS | ARG_TYPE_SWAPPABLE, // TODO swap in 0x08
ARG_INFO_MASK_30_RRS
},
{
0xc7,
0x44,
DA_LIT_neg | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xff,
0x4d,
DA_LIT_reti | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xc7,
0x45,
DA_LIT_retn | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xe7,
0x47,
DA_LIT_ld | OPCODE_TYPE_LIT,
ARG_INFO_MASK_08_IR | ARG_TYPE_SWAPPABLE, // TODO swap not working -- on bit 4 0x10
ARG_INFO_LIT_a
},
{
0xf7,
0x67,
OPCODE_BUILD_RRD | OPCODE_TYPE_BUILD,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0xc7,
0x46,
DA_LIT_im | OPCODE_TYPE_LIT,
ARG_INFO_im,
ARG_INFO_NONE
},
{
0xe4,
0xa0,
OPCODE_BUILD_LDI | OPCODE_TYPE_BUILD,
ARG_INFO_NONE,
ARG_INFO_NONE
},
{
0x00,
0x00,
DA_LIT_Q | OPCODE_TYPE_LIT,
ARG_INFO_NONE,
ARG_INFO_NONE
}
};
// sync with InstructionTableIndices
static const struct InstructionInfo* InstructionInfoTableArray[TABLE_COUNT] =
{
InstructionInfoTableMain_00,
InstructionInfoTableMain_40,
InstructionInfoTableMain_80,
InstructionInfoTableMain_c0,
InstructionInfoTableCB,
InstructionInfoTableED
};
uint8_t shiftMaskToByte(uint8_t b, uint8_t shiftMaskByte)
{
return (b >> (shiftMaskByte >> 4)) & shiftMaskByte & 0x0f;
}
static const char IM_0Q12[4] = { '0', '?', '1', '2' };
static const char* const FORMAT1C = "%c";
static const char* const FORMAT1 = "%01xh";
static const char* const FORMAT2 = "%02xh";
static const char* const FORMAT4 = "%04xh";
static const char* const FORMAT_CONTENTS = "(%s)";
uint8_t* disassemble(uint8_t* loc, char* line)
{
uint8_t b; // instruction byte being disassembled
uint8_t table = 0;
const struct InstructionInfo* entry;
bool swap = false;
uint8_t argCount = 0;
char arg0[8];
char arg1[8];
char* args[2] = { arg0, arg1 };
uint8_t opcodeInfo;
uint8_t opcodeIndex;
uint16_t offset;
uint8_t hl_ix_iy = 0;
char offsetStr[6] = { 0 };
*line = 0;
b = *loc++;
table = b >> 6;
// See if we need a special table
// 1100 1011 cb
// 1110 1101 ed
// 11-0 1--1
// 1101 1101
// 1111 1101
// 11-1 1101
if ((b & 0xdf) == 0xdd)
{
if (b == 0xdd)
{
b = *loc++;
table = b >> 6;
hl_ix_iy = 1;
}
else if (b == 0xfd)
{
b = *loc++;
table = b >> 6;
hl_ix_iy = 2;
}
}
if ((b & 0xd9) == 0xc9)
{
if (b == 0xcb)
{
b = *loc++;
table = TABLE_CB;
}
else if (b == 0xed)
{
b = *loc++;
table = TABLE_ED;
}
}
entry = InstructionInfoTableArray[table];
while (entry->mask != 0)
{
uint8_t opcodeType;
if ((b & entry->mask) == entry->value)
{
break;
}
entry++;
}
// got here so we found something to process
opcodeInfo = entry->opcodeInfo;
opcodeIndex = entry->opcodeInfo & 0x3f;
if ((opcodeInfo & 0x80) == 0)
{
if ((opcodeInfo & 0x40) == 0)
{
// OPCODE_TYPE_LIT
strcpy(line, LiteralStringArray[opcodeIndex]);
}
else
{
// OPCODE_TYPE_ARR
const struct ShiftMaskAndIndexStartInfo* opcodeByMaskInfo = &OpcodeByMaskShiftMaskArray[opcodeIndex];
uint8_t index = opcodeByMaskInfo->indexStart + shiftMaskToByte(b, opcodeByMaskInfo->shiftMaskInfo);
strcpy(line, LiteralStringArray[OpcodeByMaskArray[index]]);
}
}
else
{
// OPCODE_TYPE_BIT
buildOpcode(b, opcodeIndex, line);
}
for(argCount = 0; argCount < 2; argCount++)
{
uint8_t argInfo = (&entry->argInfoIndex0)[argCount];
char buffer[8];
const char* argText;
char* arg = args[argCount];
uint16_t argData;
const char* format = NULL;
uint8_t lit = 0xff;
bool contents = false;
// no more arguments
if (argInfo == 0)
{
break;
}
// extra info --swappable/contents
if ( ((argInfo & ARG_TYPE_SWAPPABLE) != 0) && !swap)
{
if (table < 4)
{
swap = (b & 0x08) != 0;
}
else if (table == TABLE_ED)
{
uint8_t swapMask;
// entryMask bit
// c6 0/0x01
// c7 3/0x08
// e7 4/0x10
if ((entry->mask & 0x20) == 0)
{
if ((entry->mask & 0x01) == 0)
{
swapMask = 0x01;
}
else
{
swapMask = 0x08;
}
}
else
{
swapMask = 0x10;
}
swap = (b & swapMask) != 0;
}
}
contents = (argInfo & ARG_TYPE_CONTENTS) != 0;
argInfo &= 0x3f; // remove swap/contents bits
// either set lit or argText
if (argInfo < ARG_TYPE_LIT)
{
// Specials
switch (argInfo & 0x07)
{
case ARG_INFO_rel:
argData = (uint16_t)(loc - 1) + (int8_t)(*loc);
loc++;
format = FORMAT4;
break;
case ARG_INFO_imm8:
argData = (uint8_t)(*loc);
loc++;
format = FORMAT2;
break;
case ARG_INFO_imm16:
argData = *(uint16_t*)loc;
loc += 2;
format = FORMAT4;
break;
case ARG_INFO_bit:
argData = (b >> 3) & 0x07;
format = FORMAT1;
break;
case ARG_INFO_rst:
argData = (b & 0x38);
format = FORMAT2;
break;
case ARG_INFO_im:
argData = IM_0Q12[(b & 0x18) >> 3];
format = FORMAT1C;
break;
}
sprintf(buffer, format, argData);
argText = &buffer[0];
}
else if (argInfo < ARG_TYPE_MASK)
{
// Lit
lit = ArgByLitIndexToStringLiteralIndex[argInfo & 0x0f];
}
else
{
// mask
const struct ShiftMaskAndIndexStartInfo* maskInfo = &ArgShiftMaskStartIndex[argInfo & 0x0f];
//printf("MASKINGO: %02x b: %02x -> %d\r\n", maskInfo->shiftMaskInfo, b, shiftMaskToByte(b, maskInfo->shiftMaskInfo));
lit = ArgByMaskArray[maskInfo->indexStart + shiftMaskToByte(b, maskInfo->shiftMaskInfo)];
}
// indexed lit might have the contents flag set
if ((lit != 0xff) && ((lit & ARG_TYPE_CONTENTS) != 0))
{
lit &= 0x3f;
contents = true;
}
// Convert DD/FD, hl to ix/iy and (hl) to (ix/iy+(int8_t)d)
if ((hl_ix_iy > 0) && (lit == DA_LIT_hl))
{
if (!contents || (table < 4 && b == 0xe9))
{
lit = (DA_LIT_hl + hl_ix_iy);
}
else
{
offset = (int16_t)*(int8_t*)loc++;
sprintf(buffer, "%s%c%02x", LiteralStringArray[DA_LIT_hl + hl_ix_iy], (offset < 0) ? '-' : '+', abs(offset));
argText = &buffer[0];
lit = 0xff; // switch lit out and argText in
}
}
if (lit != 0xff)
{
argText = LiteralStringArray[lit];
}
if (contents)
{
sprintf(arg, "(%s)", argText);
}
else
{
strcpy(arg, argText);
}
argInfo >>= 4;
}
if (swap)
{
args[0] = arg1;
args[1] = arg0;
}
if (argCount > 0)
{
strcat(line, " ");
strcat(line, args[0]);
}
if (argCount > 1)
{
strcat(line, ", ");
line = strcat(line, args[1]);
}
return loc;
}
Monday, October 19, 2015
Breakpoints Starting to Work
I'm finally getting breakpoints to start working!
RST 20H (0xe7) is what I use to generate breakpoints. Since the code copies itself to RAM banks and executes from RAM, the breakpoint code can swap in e7 for whatever instruction is at a certain point. This causes the execution to run off to 0x0020.
Once there, it pushes all registers. It also pushes sp (i.e. ld hl, 0; add hl, sp; push hl) and then calls a function that loads hl with a pointer to a function and jumps to it. The default function just returns. But if the pointer is modified, execution can go someplace else.
And that place is bpBreak.
The bpBreak function handles loading a pointer to the registers contents struct over the stack where the the registers are stored. That struct pointer can be used to display and change register contents. It then it replaces all the RST 20H opcodes with the original contents. While doing that, it updates the breakpoint ignore counter, deletes delete-on-break breakpoints, and deletes break-on-hit breakpoints if the pc is where the break occurred. Finally, if any breakpoint had a count of 0, it will start the break prompt, otherwise skip straight to continuing.
The break prompt is where user can interactively set, delete, and change breakpoints, view and change register contents, and view and change memory.
Step is done with temporary breakpoints that delete on break. A breakpoint usually goes at the beginning of the next instruction. The exceptions are ret, jp, and jr instructions since execution never gets beyond. Except, of course, when they are conditional. In that case, the breakpoint must be set at the destination of the jump. There are 6 possibilities of which I deal with 4;
call, jp: place breakpoint at *(uint16_t*)(bpRegs->pc+1)
jr: place breakpoint at pc+*(uint8_t*)(bpRegs->pc+1)
ret: place breakpoint at *(uint16_t*)(bpRegs->sp)
jp (hl): place breakpoint at bpRegs->hl
rst: this is not done but one could place breakpoints at 00, 08, 10, 18, 20, 28, 30, or 38
halt: this is not done but one could place a breakpoint at 66
Next is like step except if there is a call (i.e. breakpoint uses absolute addressing, may reach next instruction, and is not conditional), then the breakpoint is not placed at the destination. This fails to take into account that calls can be conditional, but the SDCC compiler is not generating conditional calls, at least at the optimization level I'm using.
Continue is a little tricky. It is assumed that the current instruction is a breakpoint. If it isn't this is overkill, but if it is, we can't just load the breakpoints and run--we'd break at the same point again. Rather, the breakpoint has be temporarily disabled, a step has to take place, and the breakpoint must be restored once past it. This is done by never loading any breakpoint at the current pc, and having the code that unloads the breakpoint determine if a break is necessary. If a deletion-break breakpoint is hit and has an ignore count greater than 0, it will not generate a break.
Here are two breakpoint files. The first is the basic breakpoint function:
This file snippet is for breakpoint prompt features:
This is the part of interrupt.c that is relevant:
RST 20H (0xe7) is what I use to generate breakpoints. Since the code copies itself to RAM banks and executes from RAM, the breakpoint code can swap in e7 for whatever instruction is at a certain point. This causes the execution to run off to 0x0020.
Once there, it pushes all registers. It also pushes sp (i.e. ld hl, 0; add hl, sp; push hl) and then calls a function that loads hl with a pointer to a function and jumps to it. The default function just returns. But if the pointer is modified, execution can go someplace else.
And that place is bpBreak.
The bpBreak function handles loading a pointer to the registers contents struct over the stack where the the registers are stored. That struct pointer can be used to display and change register contents. It then it replaces all the RST 20H opcodes with the original contents. While doing that, it updates the breakpoint ignore counter, deletes delete-on-break breakpoints, and deletes break-on-hit breakpoints if the pc is where the break occurred. Finally, if any breakpoint had a count of 0, it will start the break prompt, otherwise skip straight to continuing.
The break prompt is where user can interactively set, delete, and change breakpoints, view and change register contents, and view and change memory.
Step is done with temporary breakpoints that delete on break. A breakpoint usually goes at the beginning of the next instruction. The exceptions are ret, jp, and jr instructions since execution never gets beyond. Except, of course, when they are conditional. In that case, the breakpoint must be set at the destination of the jump. There are 6 possibilities of which I deal with 4;
call, jp: place breakpoint at *(uint16_t*)(bpRegs->pc+1)
jr: place breakpoint at pc+*(uint8_t*)(bpRegs->pc+1)
ret: place breakpoint at *(uint16_t*)(bpRegs->sp)
jp (hl): place breakpoint at bpRegs->hl
rst: this is not done but one could place breakpoints at 00, 08, 10, 18, 20, 28, 30, or 38
halt: this is not done but one could place a breakpoint at 66
Next is like step except if there is a call (i.e. breakpoint uses absolute addressing, may reach next instruction, and is not conditional), then the breakpoint is not placed at the destination. This fails to take into account that calls can be conditional, but the SDCC compiler is not generating conditional calls, at least at the optimization level I'm using.
Continue is a little tricky. It is assumed that the current instruction is a breakpoint. If it isn't this is overkill, but if it is, we can't just load the breakpoints and run--we'd break at the same point again. Rather, the breakpoint has be temporarily disabled, a step has to take place, and the breakpoint must be restored once past it. This is done by never loading any breakpoint at the current pc, and having the code that unloads the breakpoint determine if a break is necessary. If a deletion-break breakpoint is hit and has an ignore count greater than 0, it will not generate a break.
Here are two breakpoint files. The first is the basic breakpoint function:
// __asm__("rst 20h") == 0xe7
#define RST_20H ((uint8_t)(0xe7))
struct Regs* bpRegs;
struct BP bpInfo[BREAKPOINT_COUNT];
// declare fnRST_20H for telling bank 0 how to get to bpBreak
extern void(*fnRST_20H)();
// Initialize breakpoint system
void bpInit()
{
memset(bpInfo, 0, sizeof(bpInfo));
fnRST_20H = bpBreak;
}
// crt1 calls this instead of main. This calls main
void bpStart(void(*initBP)())
{
bpSet((uint8_t*)initBP, (1 << BP_FLAG_ENABLED) | (1 << BP_FLAG_DELETE_ON_HIT), 0);
bpLoadBreakPoints(NULL);
}
// Sets a breakpoint at location with behavior flags and an ignore count
uint8_t bpSet(uint8_t* location, uint8_t flags, uint8_t count)
{
uint8_t bp;
// get unusued and look for same
for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
{
struct BP* b = &bpInfo[bp];
if ((b->flags & (1 << BP_FLAG_ASSIGNED)) == 0)
{
b->flags |= (1 << BP_FLAG_ASSIGNED);
break;
}
else if (b->addr == location)
{
if (((b->flags ^ flags) & ~0x03) == 0)
{
// such a breakpoint already exists
return bp;
}
}
}
// Set the breakpoint
if (bp < BREAKPOINT_COUNT)
{
struct BP* b = &bpInfo[bp];
b->flags = flags | (1 << BP_FLAG_ASSIGNED);
b->addr = location;
b->count = count;
printf("Set BP%x @ %p (%x-%d)\r\n", bp, location, flags, count);
}
return bp;
}
// Delete a breakpoint
void bpUnset(uint8_t bp)
{
struct BP* b = &bpInfo[bp];
b->flags = 0x00;
printf("Unset BP%x @ %p (%x-%d)\r\n", bp, b->addr, b->flags, b->count);
}
// Enable or disable a breakpoint
void bpEnable(uint8_t bp, bool enable)
{
if (enable)
{
bpInfo[bp].flags |= (1 << BP_FLAG_ENABLED);
bpInfo[bp].count = 0;
}
else
{
bpInfo[bp].flags &= ~(1 << BP_FLAG_ENABLED);
}
}
// Find if a breakpoint is enabled
bool bpIsEnabled(uint8_t bp)
{
return (bpInfo[bp].flags & (1 << BP_FLAG_ENABLED)) != 0;
}
// Gets the first breakpoint at addr of 0xff
uint8_t bpAt(uint8_t* addr)
{
uint8_t bp;
for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
{
if (bpInfo[bp].addr == addr)
{
return bp;
}
}
return 0xff;
}
// Swaps in the RST 20H into the locations with breakpoints
// Breakpoints are not swapped at 'pc'
void bpLoadBreakPoints(uint8_t* pc)
{
uint8_t bp = 0;
for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
{
struct BP* b = &bpInfo[bp];
if ((b->flags & 0x03) == 0x03 && b->addr != pc) // assigned and enabled and not at PC
{
uint8_t swap = *(b->addr);
if (swap == RST_20H)
{
// already a breakpoint there
}
else
{
b->swap = swap;
*(b->addr) = RST_20H;
printf("RST 20 to %02x @ %p\r\n", b->swap, b->addr);
}
}
}
}
// Restores RST 20H with the original opcodes
// decrements ignore count for breakpoints who addr is 'pc'
// Returns whether any breakpoints at 'pc' were hit and had an ignore count of 0
bool bpUnloadBreakPoints(uint8_t* pc)
{
uint8_t bp = 0;
bool doBreak = false;
for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
{
struct BP* b = &bpInfo[bp];
if ((b->flags & (1 << BP_FLAG_ASSIGNED)) != 0)
{
if ((b->flags & (1 << BP_FLAG_ENABLED)) != 0)
{
uint8_t swap = *(b->addr);
if (swap == RST_20H)
{
printf("RST 20 from %02x @ %p\r\n", b->swap, b->addr);
*(b->addr) = b->swap;
}
if (b->addr == pc)
{
if ((b->count > 0))
{
b->count--;
}
else
{
doBreak = true;
}
// delete on hit
if ((b->flags & (1 << BP_FLAG_DELETE_ON_HIT)) != 0)
{
b->flags = 0;
}
}
}
// delete on break BP
if ((b->flags & (1 << BP_FLAG_DELETE_ON_BREAK)) != 0)
{
b->flags = 0;
}
}
}
return doBreak;
}
// This set breakpoints for certain types: 0-step 1-next 2-continue
// Step/Next: if !BRANCH_NO_STEP set bp @ pc+il
// Step: if BRANCH_ABS set @ (pc+1)
// Step: if BRANCH_REL set @ pc + (pc+1)
// Step: if BRANCH_RET set @ (sp-2)
// Step: if BRANCH_HL set @ hl
void bpStep(uint8_t type)
{
uint8_t* pc;
uint8_t branchInfo;
uint8_t instrLen;
bool breakOnNextInstr;
bool breakOnDest;
uint8_t count;
uint8_t nextFlags;
// get PC
pc = (uint8_t*)bpRegs->pc;
// get next instruction address
instrLen = z80InstructionLength(pc);
branchInfo = instrLen & 0xf8;
instrLen = instrLen & 0x07;
printf("branch %02x\r\n", branchInfo);
// figure out what to do
// if not branching away permanently, set a breakpoint there
breakOnNextInstr = (branchInfo & BRANCH_ALWAYS) == 0;
// count is 0 unless type is continue
// If count is 1, will not return to break point prompt--will just continue
count = (type == 2) ? 1 : 0;
// How flags work
// step: delete on hit for next and delete on break dest
// next: delete on hit for next
// continue: always delete on any break--restart immediately
nextFlags = (type == 2) ? (1 << BP_FLAG_DELETE_ON_BREAK) : (1 << BP_FLAG_DELETE_ON_HIT);
nextFlags |= (1 << BP_FLAG_ENABLED);
//nextFlags = (1 << BP_FLAG_DELETE_ON_BREAK) | (1 << BP_FLAG_ENABLED);
// place breakpoint if not NO_STEP branch (jp **, jp (hl), ret/i/n, jr)
if (breakOnNextInstr)
{
bpSet(pc + instrLen, nextFlags, count);
}
// BP on branch destination
breakOnDest = ((branchInfo & 0xf8) != 0);
if ((type == 1) && ((branchInfo & BRANCH_CALL) != 0))
{
breakOnDest = false; // if user is using 'next' on a call
}
if (breakOnDest)
{
uint8_t branchType = branchInfo & 0x30;
uint16_t target = 0;
// get branch addr (rel, abs, (hl), (sp-2)
if (branchType == BRANCH_ABS)
{
target = *(uint16_t*)(pc + 1);
}
else if (branchType == BRANCH_REL)
{
target = (uint16_t)pc + (int8_t)(pc[1]);
}
else if (branchType == BRANCH_RET)
{
target = *(uint16_t*)(bpRegs->sp);
}
else// if (branchType == BRANCH_HL)
{
target = bpRegs->hl;
}
// place breakpoint
bpSet((uint8_t*)target, (1 << BP_FLAG_DELETE_ON_BREAK) | (1 << BP_FLAG_ENABLED), count);
}
}
// RST 20H calls this after
void bpBreak() __naked
{
//RST_20H all registers pushed
__asm__("di");
__asm__("ld hl, #2");
__asm__("add hl, sp");
__asm__("push hl");
__asm__("ld (_bpRegs), hl");
__asm__("call _bpPrompt");
__asm__("pop hl ; toss");
__asm__("ret");
}
This file snippet is for breakpoint prompt features:
struct BpCmd {
const char* cmd;
const char* desc;
uint8_t(*fn)(const char* line);
};
void showMem(uint16_t address, uint16_t length)
{
uint8_t i;
char* ph;
char* pa;
char line[75];
w_bb shift;
address = address & 0xfff0;
length = (length + 15) & 0xfff0;
memset(line, ' ', sizeof(line) - 1);
line[sizeof(line) - 1] = 0;
line[4] = ':';
while (length)
{
shift.uw = address;
ph = &line[0];
pa = &line[4 + 1 + 1 + 1 + 16 * 3 + 1];
*ph++ = __ascii[shift.ubb.h >> 4];
*ph++ = __ascii[shift.ubb.h & 0x0f];
*ph++ = __ascii[shift.ubb.l >> 4];
*ph++ = __ascii[shift.ubb.l & 0x0f];
ph++;
ph++;
// 16 bytes
for (i = 0; i < 16; i++)
{
uint8_t b;
b = *(char*)(address + i);
*ph++ = __ascii[b >> 4];
*ph++ = __ascii[b & 0x0f];
ph++;
// unprintables to .
if (b < ' ' || b > 0x7e)
{
b = '.';
}
*pa++ = b;
// gap
if (i == 7)
{
ph++;
pa++;
}
}
puts(line);
address += 16;
length -= 16;
}
}
static void showRegs()
{
printf("af: %04x bc: %04x de: %04x hl=%04x\r\n", bpRegs->af, bpRegs->bc, bpRegs->de, bpRegs->hl);
printf("pc: %04x sp: %04x ix: %04x iy=%04x\r\n", bpRegs->pc, bpRegs->sp, bpRegs->ix, bpRegs->iy);
}
static void showBreakpoint(uint8_t bp)
{
struct BP* b = &bpInfo[bp];
printf("%x: addr=%04x en=%x count=%02x\r\n", bp, b->addr, (b->flags & (1 << BP_FLAG_ENABLED)) != 0, b->count);
}
static void showBreakpoints()
{
uint8_t i;
for (i = 0; i < BREAKPOINT_COUNT; i++)
{
struct BP* b = &bpInfo[i];
if ((b->flags & (1 << BP_FLAG_ASSIGNED)) != 0)
{
showBreakpoint(i);
}
}
}
static const struct BpCmd commands[] =
{
{
"?",
"list",
bpIntHelp
},
{
"l",
"list bp's",
bpIntList
},
{
"s",
"step",
bpIntStep
},
{
"n",
"next",
bpIntNext
},
{
"c",
"continue",
bpIntContinue
},
{
"b",
"set bp @ addr",
bpIntCreate
},
{
"d",
"delete bp # or all",
bpIntDelete
},
{
"t",
"toggle bp",
bpIntToggle
},
{
"r",
"see regs or set rr v",
bpIntRegs
},
{
"m",
"see RAM",
bpIntMem
},
};
const static uint8_t commandLength = sizeof(commands) / sizeof(commands[0]);
static uint8_t bpIntList(const char* line)
{
line; // suppress warning
showBreakpoints();
return 0;
}
static uint8_t bpIntHelp(const char* line)
{
uint8_t i;
line; // suppress warning
for (i = 0; i < commandLength; i++)
{
printf("%s - %s\r\n", commands[i].cmd, commands[i].desc);
}
return 0;
}
static uint8_t bpIntContinue(const char* line)
{
line; // suppress warning
bpStep(2);
return 0xff; // continue
}
static uint8_t bpIntStep(const char* line)
{
line; // suppress warning
bpStep(0);
return 0xff; // continue
}
static uint8_t bpIntNext(const char* line)
{
line; // suppress warning
bpStep(1);
return 0xff; // continue
}
static uint8_t bpIntCreate(const char* line)
{
if (*line++ == ' ')
{
uint16_t addr = extractHex(&line);
uint8_t count = 0;
if (*line == ' ')
{
line++;
count = extractHex(&line);
}
if (*line == 0)
{
uint8_t i = bpSet((uint8_t*)addr, (1<<BP_FLAG_ENABLED), count);
if (i == 0xff)
{
puts("BP full");
return 1;
}
else
{
showBreakpoint(i);
}
}
else
{
return 2;
}
}
else
{
return 3;
}
return 0;
}
static uint8_t bpIntDelete(const char* line)
{
uint8_t status = 0;
if (*line == ' ')
{
uint8_t i;
line++;
i = extractHex(&line);
if (*line == 0 && i < BREAKPOINT_COUNT)
{
bpUnset(i);
}
}
return 0;
}
static uint8_t bpIntToggle(const char* line)
{
//uint8_t status = 0;
uint8_t bp;
if (*line == ' ')
{
bp = extractHex(&line);
}
else if (*line == 0)
{
bp = bpAt((uint8_t*)bpRegs->pc);
}
else
{
return 1;
}
if (bp >= BREAKPOINT_COUNT)
{
return 2;
}
bpEnable(bp, !bpIsEnabled(bp));
showBreakpoint(bp);
return 0;
}
static const char* const regs = "SPiyixhldebcafpc";
static uint8_t bpIntRegs(const char* line)
{
//uint8_t status = 0;
if (*line == 0)
{
showRegs();
return 0;
}
else if (*line == ' ')
{
uint8_t i;
uint16_t search;
const uint16_t* reg = (const uint16_t*)regs;
line++;
search = *(uint16_t*)line;
for (i = 0; i < 7; i++)
{
if (search == *reg)
{
uint16_t val;
line += 3;
val = extractHex(&line);
if (*line == 0)
{
((uint16_t*)bpRegs)[i] = val;
showRegs();
}
else
{
puts("?");
}
}
reg++;
}
}
return 0;
}
static uint8_t bpIntMem(const char* line)
{
uint16_t addr = 0;
uint16_t len = 16;
if (*line++ == ' ')
{
addr = extractHex(&line);
if (*line++ == ' ')
{
len = extractHex(&line);
}
if (*line == 0)
{
showMem(addr, len);
return 0;
}
}
return 1;
}
// do prompt for breaks
// ? list commands
// l list breakpoints
// c continue
// s step
// n next
// b xxxx (cc) break @ xxxx (optional countdown)
// d ## delete ##
// t ## toggle ## enable
// r show regs
// r rr xxxx set reg (except sp)
// m xxxx xxxx show mem
void bpPrompt()
{
char buffer[32];
char* p;
uint8_t i;
uint16_t pc = bpRegs->pc - 1; // source of RST_20
uint8_t interruptSave;
bool doBreak;
bpRegs->pc = pc; // restore to the instruction that was supposed to be there
doBreak = bpUnloadBreakPoints((uint8_t*)pc);
interruptSave = ei_save();
while (doBreak)
{
uint8_t result = 0;
char c;
printf("(brk @ %p)> ", pc);
gets(buffer);
p = &buffer[0];
c = *p;
for (i = 0; i < commandLength; i++)
{
const char* cmd = commands[i].cmd;
uint8_t len = strlen(cmd);
if (strncmp(commands[i].cmd, p, len) == 0)
{
result = commands[i].fn(&p[len]);
}
}
if (result == 0xff)
{
break;
}
else if (result != 0)
{
printf("error %d\r\n", result);
}
}
bpLoadBreakPoints((uint8_t*)pc);
di_restore(interruptSave);
}
This is the part of interrupt.c that is relevant:
static void ret() __naked
{
__asm__("ret");
}
// This is preset to 'ret' If the code runs frojmj flash, this is necessary.
// If the code runs from RAM, this can be overridden.
void(*fnRST_20H)() = ret;
static void call_hl() __naked
{
__asm__("jp (hl)");
}
void do_RST_20H() __naked
{
__asm__("push af");
__asm__("push bc");
__asm__("push de");
__asm__("push hl");
__asm__("push ix");
__asm__("push iy");
// push sp
__asm__("ld hl, #14");
__asm__("add hl, sp");
__asm__("push hl");
__asm__("ld hl, (_fnRST_20H)");
__asm__("call _call_hl");
__asm__("pop iy"); // toss SP
__asm__("pop iy");
__asm__("pop ix");
__asm__("pop hl");
__asm__("pop de");
__asm__("pop bc");
__asm__("pop af");
__asm__("ret");
}
Z-80 Instruction Lengths
In order to handle breakpoints functionality of step, next, and continue, it is necessary to know 1) how long the current instruction is and 2) whether and how it branches.
So I coded up a quick function that takes a pointer to a location and returns 1) 1-4 in the lower 3 bits with instruction length, 2 bits with the branch type (absolute, relative, return, and jp (hl)), one bit to indicate the branch is conditional, and one bit for instructions that always branch away and will never get to the next instruction.
Note that the 'rst' and 'halt' commands don't have branch information. Anyone wanting to try to use this code will want to add that if they need it.
Here it is:
So I coded up a quick function that takes a pointer to a location and returns 1) 1-4 in the lower 3 bits with instruction length, 2 bits with the branch type (absolute, relative, return, and jp (hl)), one bit to indicate the branch is conditional, and one bit for instructions that always branch away and will never get to the next instruction.
Note that the 'rst' and 'halt' commands don't have branch information. Anyone wanting to try to use this code will want to add that if they need it.
Here it is:
// The following are found in pBranchInfo
#define BRANCH_CALL (0x08)
// relative to pc + (int8_t)(opcode+1) ALWAYS or COND
#define BRANCH_REL (0x20)
// absolute to (void*)(opcode+1) ALWAYS or COND
#define BRANCH_ABS (0x10)
// return to (void*)(sp-2) ALWAYS or COND
#define BRANCH_RET (0x30)
// to (hl) // ALWAYS but never COND
#define BRANCH_HL (0x00)
// conditional--bp necessary after instruction
#define BRANCH_COND (0x40)
// always--will never got to pc+length--certain to branch
#define BRANCH_ALWAYS (0x80)
struct InstLen
{
uint8_t mask;
uint8_t value;
uint8_t data;
};
static const struct InstLen scan00[] =
{
// ld rr, **
{
0xcf, 0x01, 3
},
// ld (hl)/a <-> **
{
0xe7, 0x22, 3
},
// ld r, *
{
0xc7, 0x06, 2
},
// jr f, *
{
0xe7, 0x20, 2 | BRANCH_REL | BRANCH_COND
},
// djnz *
{
0xff, 0x10, 2 | BRANCH_REL | BRANCH_COND
},
// jr *
{
0xff, 0x18, 2 | BRANCH_REL | BRANCH_ALWAYS
},
};
static const struct InstLen scan11[] =
{
// ret f (not detault b/c branch)
{
0xc7, 0xc0, 1 | BRANCH_RET | BRANCH_COND
},
// ret (not detault b/c branch)
{
0xff, 0xc9, 1 | BRANCH_RET | BRANCH_ALWAYS
},
// jp (hl)
{
0xff, 0xe9, 1 | BRANCH_HL | BRANCH_ALWAYS
},
// jp f, **
{
0xc7, 0xc2, 3 | BRANCH_ABS | BRANCH_COND
},
// call f, **
{
0xc7, 0xc4, 3 | BRANCH_ABS | BRANCH_COND | BRANCH_CALL
},
// jp **
{
0xff, 0xc3, 3 | BRANCH_ABS | BRANCH_ALWAYS
},
// call **
{
0xff, 0xcd, 3 | BRANCH_ABS | BRANCH_CALL
},
// arith *, *
{
0xc7, 0xc6, 2
},
// out/in(*), a
{
0xf7, 0xd3, 2
},
// bit op
{
0xff, 0xcb, 2
}
};
static const struct InstLen scanED[] =
{
// ld (rr) <-> **
{
0xc7, 0x43, 4
}
};
static const struct InstLen scanDDFD[] =
{
// ld ix, **
{
0xff, 0x21, 4
},
// ld ix <-> (**)
{
0xf7, 0x22, 4
},
// ld (ix+*), * order dep
{
0xff, 0x36, 4
},
// various
{
0x07, 0x06, 3
},
// ld (ix+*), r
{
0xb8, 0x30, 3
},
// bit ops
{
0xff, 0xcb, 3
},
};
// Returns the length in the first 3 bits and the BRANCH_* bits in the upper 5 bits
uint8_t z80InstructionLength(uint8_t* start)
{
uint8_t opcode = *start++;
const struct InstLen* scanner;
int i;
uint8_t length;
uint8_t instructionLength = 1;
if ((opcode & 0x80) == 0)
{
if ((opcode & 0x40) == 0)
{
scanner = scan00;
length = sizeof(scan00) / sizeof(scan00[0]);
}
else
{
return 1;
}
}
else
{
if ((opcode & 0x40) == 0)
{
return 1;
}
else
{
if ((opcode & 0xdf) == 0xdd)
{
scanner = scanDDFD;
length = sizeof(scanDDFD) / sizeof(scanDDFD[0]);
instructionLength = 2;
opcode = *start++;
}
else if (opcode == 0xed)
{
scanner = scanED;
length = sizeof(scanED) / sizeof(scanED[0]);
instructionLength = 2;
opcode = *start++;
}
else
{
scanner = scan11;
length = sizeof(scan11) / sizeof(scan11[0]);
}
}
}
for (i = 0; i < length; i++)
{
const struct InstLen* scan = &scanner[i];
if ((scan->mask & opcode) == scan->value)
{
instructionLength = scan->data;
break;
}
}
return instructionLength;
}
Friday, October 9, 2015
Update
I've been working on testing the vector which allows me to have library (C/driver) functions in bank 0 and separately compile a program in bank 1 that links to a vector that just forwards the calls from bank 1 to the right place in bank 0. I've found a few issues but for the most part it works as expected.
Also, I have coded but not yet started testing the breakpoint code. All it does now is create/delete/enable/disable breakpoints, show/set registers, and dump memory. Step and next require getting the size of the current instruction as well as the possible branch destination. So that's still on the back burner.
Well, off to start testing the debug code....
Also, I have coded but not yet started testing the breakpoint code. All it does now is create/delete/enable/disable breakpoints, show/set registers, and dump memory. Step and next require getting the size of the current instruction as well as the possible branch destination. So that's still on the back burner.
Well, off to start testing the debug code....
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